Masterclock TCDS Series Especificações Página 1

4 ADC with PLL, 192 kHz, 24-Bit ADC Data Sheet AD1974 Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate

AD1974 Data Sheet Rev. D | Page 10 of 24 TYPICAL PERFORMANCE CHARACTERISTICS 0.100.080.060.040.020–0.10–0.08–0.06–0.04–0.020 1800016000140001200010

Data Sheet AD1974 Rev. D | Page 11 of 24 THEORY OF OPERATIONANALOG-TO-DIGITAL CONVERTERS (ADCS) There are four ADC channels in the AD1974 configured

AD1974 Data Sheet Rev. D | Page 12 of 24 Table 11. Standalone Mode Selection ADC Clocks CIN COUT CCLK CLATCH Slave 0 0 0 0 Master 0 1 0 0 D0

Data Sheet AD1974 Rev. D | Page 13 of 24 TDM MODES The AD1974 serial ports also have several different TDM serial data modes. The first and most comm

AD1974 Data Sheet Rev. D | Page 14 of 24 LEFT RIGHTMSB MSBMSB MSBMSBADCL1 ADCR1 ADCL2 ADCR2 AUXL1 AUXR1 AUXL2 AUXR2 UNUSED UNUSED UNUSED UNUSEDUNUSED

Data Sheet AD1974 Rev. D | Page 15 of 24 ALRCLKABCLKFOUR ADC CHANNELS OFTHE SECOND IC IN THE CHAINFOUR ADC CHANNELS OFTHE FIRST IC IN THE CHAINADCL1

AD1974 Data Sheet Rev. D | Page 16 of 24 06614-014AUXBCLKAUXRCLKAUXDATALEFT JUSTIFIEDMODEAUXDATARIGHT JUSTIFIEDMODEAUXDATAI2S JUSTIFIEDMODEtXDHtXDHtX

Data Sheet AD1974 Rev. D | Page 17 of 24 AUXADC 1LRCLKBCLKDATAMCLKAUXADC 2LRCLKBCLKDATAMCLK30MHz12.288MHzSHARC IS RUNNINGIN SLAVE MODE(INTERRUPT-DRIV

AD1974 Data Sheet Rev. D | Page 18 of 24 CONTROL REGISTERS The global address for the AD1974 is 0x04, shifted left one bit due to the R/W bit. All

Data Sheet AD1974 Rev. D | Page 19 of 24 Table 17. PLL and Clock Control 1 Bit Value Function Description 0 0 PLL clock AUXPORT clock source

AD1974 Data Sheet Rev. D | Page 2 of 24 TABLE OF CONTENTS Features ...

AD1974 Data Sheet Rev. D | Page 20 of 24 Table 20. AUXPORT Control 2 Bit Value Function Description 0 0 Reserved 1 Reserved 2:1 00 Reserv

Data Sheet AD1974 Rev. D | Page 21 of 24 Bit Value Function Description 6:5 00 Stereo Serial format 01 TDM (daisy chain) 10 ADC AUX mode (TD

AD1974 Data Sheet Rev. D | Page 22 of 24 ALRCLKABCLKASDATA1DATA MUST BE VALIDAT THIS BCLK EDGEMSB06614-060 Figure 16. I2S Pipeline Mode in ADC Seria

Data Sheet AD1974 Rev. D | Page 23 of 24 APPLICATION CIRCUITSTypical applications circuits are shown in Figure 17 and Figure 18. Figure 17 shows a ty

AD1974 Data Sheet Rev. D | Page 24 of 24 OUTLINE DIMENSIONS COMPLIANT TO JEDEC STANDARDS MS-026-BBCTOP VIEW(PINS DOWN)1121325243637480.270.220.170.50

Data Sheet AD1974 Rev. D | Page 3 of 24 SPECIFICATIONS TEST CONDITIONS Performance of all channels is identical, exclusive of the interchannel gain

AD1974 Data Sheet Rev. D | Page 4 of 24 Specifications measured at 125°C (case). Table 2. Parameter Conditions Min Typ Max Unit ANALOG-TO-DIGI

Data Sheet AD1974 Rev. D | Page 5 of 24 POWER SUPPLY SPECIFICATIONS Table 5. Parameter Conditions/Comments Min Typ Max Unit SUPPLIES Volt

AD1974 Data Sheet Rev. D | Page 6 of 24 Parameter Condition Comments Min Max Unit PLL Lock Time MCLK and LRCLK input 10 ms 25

Data Sheet AD1974 Rev. D | Page 7 of 24 ABSOLUTE MAXIMUM RATINGSTable 8. Parameter Rating Analog (AVDD) −0.3 V to +3.6 V Digital (DVDD) −0.3 V t

AD1974 Data Sheet Rev. D | Page 8 of 24 PIN CONFIGURATION AND FUNCTION DESCRIPTIONSAVDD48LF47ADC2RN46ADC2RP45ADC2LN44ADC2LP43ADC1RN42ADC1RP41ADC1LN4

Data Sheet AD1974 Rev. D | Page 9 of 24 Pin No. Type1 Mnemonic Description 44 I ADC2LN ADC2 Left Negative Input. 45 I ADC2RP ADC2 Right Pos